1. Field of the Invention
The invention relates to a method and an apparatus for the analysis of scratches on semiconductor wafers.
2. Description of the Related Art
Electronics is nowadays dominated by microelectronic components with integrated circuits. Such integrated circuits represent a functional unit, which are characterized by a multiplicity of electronic functional elements having dimensions in the micron and sub-micron range and which are electrically and mechanically inseparably connected to one another. The electronic functional elements are realized on a common semiconductor substrate.
The fabrication of integrated circuits is essentially subdivided into three large stages: the production of the semiconductor slice (substrate), the fabrication of the individual chips on the semiconductor slice, also called the wafer hereinafter, and the final mounting of the individual chips. In this case, the standard method for producing the chips on the semiconductor slice is the planar technique. This is understood to be the simultaneous production of a large number of functional elements and the electrical interconnection thereof on a planar semiconductor slice. The individual steps can be classified in four large process groups, namely layer production, lithography, etching and doping, the process groups in each case preferably being processed in the aforesaid order in multiple cyclic repetition.
Several hundred individual steps are necessary to form large scale integrated circuits in the context of chip fabrication, in which case the semiconductor slices, or groups of semiconductor slices, also called batches hereinafter, often have to be transferred between the process installations that perform the respective individual steps, this usually being effected with the aid of automatic handling and mounting units. During this transfer of the semiconductor slices or of the batches with semiconductor slice surfaces, defects may arise on the semiconductor slices. According to experience, 0.1% of the wafers are damaged by the handling of the wafers in the process installations or during the transport between the process installations. In particular, the handling units often cause large scratches on the rear sides of the wafers during the transfer of the wafers, which scratches may bring about wafer fractures and thus a stoppage of the process installation. Such a stoppage of the process installations then leads to the outage of fabrication capacity and at the same time to the loss of the wafer. Defects caused by the process installations are also increasingly gaining in importance because the diameters of the semiconductor slices, and thus the risk of fracture, are increasing. Furthermore, for cost reasons it is an objective to continually increase the wafer throughput in chip fabrication.
In order to minimize the disturbance in chip fabrication on account of production-installation-specific scratches, in particular on the rear side of wafers, it is necessary to rapidly and actively search for causes and to correspondingly detect defects, in particular scratches. Hitherto, the search for causes has been effected by means of a surface inspection of the processed semiconductor slices and the subsequent attempt to correlate the defects that occur with the process installations causing the defects. However, such installation correlation proves to be difficult in particular when a fault image occurs only at a small number of wafers. In order to determine the fault cause, it is furthermore possible to carry out test runs with bare slices in order to determine the process installation causing the fault. However, this is time-consuming and expensive and furthermore leads to a production installation stop during chip fabrication.